
Phase Locked Loop Chip
Phase-Locked Loop (PLL) is a feedback circuit designed to allow one circuit board to synchronize the phase of its on board clock with an external timing signal
Designator | Part Number | Value | Voltage - Rated | Footprint | |
1 | Phase Detector(PD) | RAZPL186 | Phase Identification Frequency: 0.1~1.3GHz RF Input Frequency: 0.1~1.3GHz RF Frequency Division Number: 1 Phase Noise(fpd=100MHz): -155dBc/Hz@100KHz Working Current: 115mA |
3.3V | Die |
2 | Fractional-N PLL | RAZPL194SP4 | Phase Identification Frequency: 16~125MHz@Decimal Mode 16~150MHz@Integer Mode RF Input Frequency: 1.3~15GHz@The Front 2-Way On 0.5~5GHz@The Front 2-Way Off N-Division Ratio: 32~1048574@The Front 2-Way On 16~524287@The Front 2-Way Off Noise Fom(fpd=100MHz): -223dBc/Hz |
3.3V | 4*4 QFN-24L |
3 | Fractional-N PLL | RAZPL219SP4 | Phase Identification Frequency: 1~300MHz@Integer Mode 5~150MHz@Decimal Mode RF Input Frequency: 0.2~25GHz@Integer Mode 0.2~18GHz@Decimal Mode N-Division Ratio: 20~32768@Integer Mode 24~32768@Decimal Mode Noise Fom(fpd=100MHz): -232dBc/Hz@Integer Mode -225dBc/Hz@Decimal Mode |
3.3V | 4*4 QFN-24L |
4 | Integrated VCO PLL | SITR229SP4C | Frequency: 23~25GHz Power Input: -25~20dBm Phase Identification Frequency:16~125MHz@Decimal Mode 16~150MHz@Integer Mode R-Division Ratio: 1~16383 SNR: -220dBc/Hz |
4*4 QFN-32L |